Diakopto announced today that Silicon Creations® has selected ParagonX™ to improve the design quality, productivity, and time-to-market for their industry-leading portfolio of analog and mixed-signal intellectual property (IP).
ParagonX accelerates the analysis, debugging and optimization of integrated circuits (IC) design challenges caused by layout parasitics. By providing actionable insights to help engineers quickly and easily pinpoint bottlenecks and root causes, ParagonX helps Silicon Creations enhance the performance, power, robustness, and reliability of their suite of precision and general-purpose timing PLLs, oscillators, low-power, high-performance SerDes and high-speed differential I/Os.
Jeff Galloway, Co-founder and CTO, Silicon Creations commented, “Silicon Creations is designing PLLs and SerDes from 3nm to 180nm. As the geometries get finer, parasitics become more important. We’re using ParagonX to help analyze and optimize these parasitics to improve our designs.” He added, “ParagonX has many powerful features that both designers and layout engineers can use to analyze the design. Its visualization capability has been a very effective way for designers and layout engineers to communicate about the parasitics affecting design performance.”
Parasitics are unintended elements in IC designs that degrade circuit performance, precision, power efficiency, robustness, and reliability. The ever-increasing need for higher density, faster speed, and greater precision of integrated circuits, coupled with continued migration to more advanced technology nodes have redefined the role of parasitics in IC design. The power-performance-area (PPA) metric and time-to-market of modern ICs are now dominated by on-chip interconnects and layout parasitics. Debugging the root causes of IC design problems has become extraordinarily difficult, tedious, and time-consuming.
ParagonX offers a new methodology that treats parasitics as a first-order design parameter. It is orders of magnitude faster and offers deep insight to help users quickly find the proverbial needle in a haystack – the few critical parasitic elements (out of thousands, millions, or billions) that are responsible for bottlenecks, choke points and weak areas. This reduces parasitics-related IC debugging and optimization time from days or weeks to minutes or hours, which is especially valuable during the tapeout phase.
Maxim Ershov, Diakopto co-founder, CEO and CTO commented, “ParagonX is a perfect complement to Silicon Creations’ rigorous design methodology. We are thrilled to have them join our growing customer base, and to have ParagonX as a key enabler in continuing their excellent record of first silicon to mass production in customer designs.”
ParagonX features a robust set of tools for rapid electrical, capacitive, structural, connectivity and net-matching analysis and visualization. Information showing the most and least critical areas to be fixed are highlighted on the circuit layout, enabling designers to see where trade-offs can be made to optimize power, performance, and area. ParagonX helps reduce IC debugging and optimization time from days or weeks down to minutes or hours.
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