Data-Analytics-Driven Platform Enables Critical Improvement in Performance, Reliability, Functional Safety and Security
- Increasing chip and system complexity, coupled with growing performance and reliability requirements, are driving the need for ongoing post-silicon analysis, maintenance and optimization
- The Synopsys SLM platform closes the silicon loop through the analysis of on-chip monitor and sensor data to optimize all phases of the silicon lifecycle
- Potential financial benefits from improvements in performance, reliability and functional safety in industries such as data centers and automotive are measured in the billions of dollars
- New expanded TAM opportunity builds on Synopsys’ leadership in chip and system design, verification, test, design IP and long-standing links to manufacturing
Synopsys, Inc. (Nasdaq: SNPS) today, in a move that expands its industry leadership throughout the design lifecycle, unveiled its Silicon Lifecycle Management (SLM) platform, the industry’s first data-analytics-driven approach to optimizing SoCs from the design phase through to end-user deployment. The SLM platform, which is tightly coupled with Synopsys’ market-leading Fusion Design Platform, will provide visibility into critical performance, reliability and security issues for the entirety of a chip’s lifespan. It will enable new levels of insights for both SoC teams and their customers and provide the ability to optimize operational activities at each stage of the device and system lifecycles.
“Like so many other business domains today, the semiconductor industry now has the opportunity to further leverage empirical data about its products and technologies in order to achieve efficiencies across the electronics value chain, including at the system-level deployment stage,” said Sassine Ghazi, chief operating officer of Synopsys. “Building on our core expertise in IC design, our SLM platform provides a game-changing set of optimization capabilities that extend throughout the entire lifecycle of IC design, production and deployment.”
The growing complexity of today’s electronics systems is making quality and reliability increasingly difficult to achieve. This, coupled with little tolerance for performance degradation of any kind and the need to meet functional safety and security requirements, means that a new approach is needed to address how silicon-based systems are developed, operated and maintained. The potential gains and cost savings in key applications like data centers and networking from improvements in performance and power could be measured in the billions of dollars. These savings can be achieved by properly managing each phase of a chip’s and system’s lifecycle from development through deployment to ensure optimized results throughout.
“Addressing critical chip performance and reliability issues is a multi-billion dollar issue that doesn’t stop at tape out. It requires a new way of looking at the entirety of how an IC is designed, built and used. Providing access to device data throughout the entire chip life span, and enabling on-going ‘in life’ feedback and optimization through specialized analytics will allow a more efficient and effective way to address the semiconductor-related quality and security challenges system companies face in all industries,” said Richard Wawrzyniak, Principal Market Analyst: ASIC & SoC, Semico Research Corp.
The Synopsys SLM platform, launched today and with a full roadmap of innovation over the next two years, is based on two underlying principles: gather as much useful data about each chip as possible and analyze that data throughout its entire lifecycle to gain actionable insights into improving chip and system-related activities. The first principle is achieved by expanding upon the data already available from test and product engineering with deep visibility into each chip’s operation through monitors and sensors that are embedded throughout each chip and measure targeted activities across a wide set of contexts and conditions. The second SLM platform principle is to apply targeted analytics engines that operate on available chip data to enable optimizations at each stage of the semiconductor lifecycle, starting with design implementation, and progressing through manufacturing, production test, bring-up and culminating with in-field operation.